Introduction to information theory
Introduction to information theory
Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Data compression (3rd ed.): techniques and applications: hardware and software considerations
Data compression (3rd ed.): techniques and applications: hardware and software considerations
Elements of information theory
Elements of information theory
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
An efficient finite-state machine implementation of Huffman decoders
Information Processing Letters
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
Mathematics for the Analysis of Algorithms
Mathematics for the Analysis of Algorithms
Test Width Compression for Built-In Self Testing
Proceedings of the IEEE International Test Conference
An Efficient Method for Compressing Test Data
Proceedings of the IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A self-driven test structure for pseudorandom testing of non-scan sequential circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
4.1 COMPACT: A Hybrid Method for Compressing Test Data
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
PROOFS: a super fast fault simulator for sequential circuits
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of built-in test generator circuits using width compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
Test Resource Partitioning for SOCs
IEEE Design & Test
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Proceedings of the 18th ACM Great Lakes symposium on VLSI
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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We present a new pattern generation approach fordeterministic built-in self testing (BIST) of sequential circuits.Our approach is based on precomputed test sequences, and isespecially suited to sequential circuits that contain a large numberof flip-flops but relatively few controllable primary inputs. Suchcircuits, often encountered as embedded cores and as filters fordigital signal processing, are difficult to test and require longtest sequences. We show that statistical encoding of precomputedtest sequences can be combined with low-cost pattern decoding toprovide deterministic BIST with practical levels of overhead. OptimalHuffman codes and near-optimal Comma codes are especially usefulfor test set encoding. This approach exploits recent advances inautomatic test pattern generation for sequential circuits and, unlikeother BIST schemes, does not require access to a gate-level model ofthe circuit under test. It can be easily automated and integratedwith design automation tools. Experimental results for the ISCAS 89benchmark circuits show that the proposed method provides higherfault coverage than pseudorandom testing with shorter testapplication time and low to moderate hardware overhead.