Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA

Authors:
A. Benkrid;D. Crookes;K. Benkrid
Affiliations:
The Queen's University of Belfast, Belfast, UK;The Queen's University of Belfast, Belfast, UK;The Queen's University of Belfast, Belfast, UK
Venue:
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Year:
2003

Citing 0
Cited 1

Handling finite length signals borders in two-channel multirate filter banks for perfect reconstruction

Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper gives a design framework for the implementation of the 2-D Orthogonal Discrete Wavelet Transform (DWT) on FPGA. The architecture is based on the Pyramid Algorithm Analysis. Our architecture spatially maps the multistage filter banks of the DWT onto the Xilinx Virtex-E FPGA family. In this paper we propose a novel FIR structure to handle the computation along the borders using symmetric extension. The paper includes a new detailed mathematical approach to determine the architecture's dynamic range as well as predicting and reducing the error dynamic range due to wordlength rounding. For an NxN image size input, our architecture has a period of N2 clock cycles, and requires only the minimum storage size. The architecture is highly scalable for different filter lengths and number of octaves. The implementation results for a specific 2-D Daubechies-4 Wavelet Transform are included.