Lattice adaptive filter implementation for FPGA

Authors:
Zdenek Pohl;Rudolf Matoušek;Jirí Kadlec;Milan Tichý;Miroslav Lícko
Affiliations:
Institute of Information Theory and Automation, CAS;Institute of Information Theory and Automation, CAS;Institute of Information Theory and Automation, CAS;Institute of Information Theory and Automation, CAS;Faculty of Electrical Engineering, CTU
Venue:
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Year:
2003

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Abstract

Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our approach is based on arithmetic using logarithmic numeric representation (LNS). The test application - an adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. The filter orders up to 252 at 7 kHz sampling frequency have been achieved using the 19-bit LNS arithmetic. The maximum performance of the application is about 70 MFLOPs including i/o conversions. It has been shown that the custom filter design can be 10 times faster than commonly used solutions. This work was supported by the Ministry of Education of the Czech Republic under Project No. LN00B06.