Evaluating the performance of four snooping cache coherency protocols
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Adaptive cache coherency for detecting migratory shared data
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Limitations of cache prefetching on a bus-based multiprocessor
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Simple compiler algorithms to reduce ownership overhead in cache coherence protocols
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Effective cache prefetching on bus-based multiprocessors
ACM Transactions on Computer Systems (TOCS)
Tolerating latency through software-controlled data prefetching
Tolerating latency through software-controlled data prefetching
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A compiler algorithm that reduces read latency in ownership-based cache coherence protocols
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Predicting data cache misses in non-numeric applications through correlation profiling
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned
Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned
Distributed Shared Memory: Concepts and Systems
Distributed Shared Memory: Concepts and Systems
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
Sequential Hardware Prefetching in Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Dynamic decentralized cache schemes for mimd parallel processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Two techniques for improving performance on bus-based multiprocessors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Cache Injection on Bus Based Multiprocessors
SRDS '98 Proceedings of the The 17th IEEE Symposium on Reliable Distributed Systems
Hardware-Based Load Value Trace Filtering for On-the-Fly Debugging
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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In bus-based SMPs, cache misses and bus traffic form key obstacles to high performance. To overcome these problems, several techniques have been proposed: cache prefetching, read snarfing, software-controlled updating, and cache injection for reducing cache misses, and migrate-on-dirty, adaptive migratory detection, load-exclusive instruction, and exclusive prefetching for reducing invalidation bus traffic.