Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters

  • Authors:

  • Masaki Tsukude;Kazutami Arimoto;Hideto Hidaka;Yasuhiro Konishi;Masanori Hayashikoshi;Katsuhiro Suma;Kazuyasu Fujishima

  • Affiliations:

  • -;-;-;-;-;-;-

  • Venue:
  • IEEE Design & Test
  • Year:
  • 1993

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Abstract

Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V/sub CC/ levels during the water sort test (WT) and the final shipping test (FT).