How RISCy is DSP?

Authors:
Michael R. Smith
Affiliations:
-
Venue:
IEEE Micro
Year:
1992

Citing 3
Cited 0

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DFT/FFT and Convolution Algorithms: Theory and Implementation

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Abstract

The characteristics of benchmark digital signal processing (DSP) algorithms are examined. These characteristics are used to suggest the features of an ideal DSP architecture, which is compared to current DSP and reduced instruction set computer (RISC) architectures. Timing comparisons taken from data books and research show that several on-the-market RISCs have a DSP performance close to or better than some DSP chips. Analysis of these DSP and RISC architectures leads to the suggestion of an ideal low-cost RISC DSP chip.