An ASIC Chip Set for Parallel Fuzzy Database Mining

Authors:
Alberto Ferrari;Antonella Bellettini;Roberto Guerrieri;Giorgio Baccarani
Affiliations:
-;-;-;-
Venue:
IEEE Micro
Year:
1996

Citing 5
Cited 1

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Abstract

This paper describes the design and implementation of an application-specific digital architecture aimed at performing the mining of fuzzy databases, a task whose computational weight is very high. The system described here is an array-processor architecture in which the database is split into several units that apply the same operations to different data stored in local memories at the same time. A chip set implementing the architecture has been built using a semicustom approach and it is fully functional. The sustained memory bandwidth of a system featuring 16 units is 5,120 Mbits/s and provides a speedup of 500 times over the software algorithm running on a Sun Sparc2 workstation.