Computer
Coherency for multiprocessor virtual address caches
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
On the inclusion properties for multi-level cache hierarchies
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Translation lookaside buffer consistency: a software approach
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Organization and performance of a two-level virtual-real cache hierarchy
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Consistency management for virtually indexed caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Eliminating the address translation bottleneck for physical address cache
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
MIPS R4000 user's manual
Multiprocessor system architectures
Multiprocessor system architectures
Evolution of the PowerPC Architecture
IEEE Micro
Sharing and protection in a single-address-space operating system
ACM Transactions on Computer Systems (TOCS) - Special issue on computer architecture
The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Operating Systems Theory
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
Converting a swap-based system to do paging in an architecture lacking page-referenced bits
SOSP '81 Proceedings of the eighth ACM symposium on Operating systems principles
U-cache: a cost-effective solution to synonym problem
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
The IBM 3090 system: an overview
IBM Systems Journal
Options for dynamic address translation in COMAs
Proceedings of the 25th annual international symposium on Computer architecture
Tolerating late memory traps in ILP processors
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
IEEE Transactions on Computers
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Tolerating Late Memory Traps in Dynamically Scheduled Processors
IEEE Transactions on Computers
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Enigma: architectural and operating system support for reducing the impact of address translation
Proceedings of the 24th ACM International Conference on Supercomputing
Reducing memory reference energy with opportunistic virtual caching
Proceedings of the 39th Annual International Symposium on Computer Architecture
Regional cache organization for NoC based many-core processors
Journal of Computer and System Sciences
A new perspective for efficient virtual-cache coherence
Proceedings of the 40th Annual International Symposium on Computer Architecture
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In order to support virtual memory, virtual addresses must be efficiently translated into physical addresses. Traditionally, this dynamic translation has been done in a Translation Lookaside Buffer (TLB) before or in parallel with the cache access, so that the cache is indexed and tagged with physical addresses. Consistency problems add complexity to virtual-address caches. The main sources of these problems are the presence of synonyms and address-mapping changes. In this first part of this two-part survey, we introduced the problems and discussed solutions in the context of single-processor systems. In Part 2 of, we address multiprocessor issues. In multiprocessors, coherence of caches and TLBs must be maintained. The virtual caches can take advantage of these mechanisms. Therefore, some solutions make more sense than others in a multiprocessor environment.