The 82460GX Sever/Workstation Chip Set

Authors:
Eric Dahlen;Jennifer Gustin;Susan Meredith;Doug Moran
Affiliations:
-;-;-;-
Venue:
IEEE Micro
Year:
2000

Citing 2
Cited 2

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Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors

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Abstract

This article provides an introduction to the memory, I/O, and graphics subsystems of Intel's Itanium processor chip set and discusses several aspects of the processor bus.