An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor

Authors:
G. F. Taylor;R. H. Steinvorth;J. F. McDonald
Affiliations:
Bipolar Integrated Technology, Beaverton, OR;San Jose Univ., San Jose, Costa Rica;Rensselaer Polytechnic Institute, Troy, NY
Venue:
IEEE Transactions on Computers
Year:
1988

Citing 1
Cited 4

An Adaptation of the Fast Fourier Transform for Parallel Processing

Journal of the ACM (JACM)

Amdahl's law and end of system design

ACM SIGMETRICS Performance Evaluation Review
A Weighted Z Spectrum, Parallel Algorithm, and Processors for Mathematical Model Estimation

IEEE Transactions on Computers
Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis

IEEE Transactions on Computers
Efficient 2D FFT implementation on mediaprocessors

Parallel Computing

Quantified Score

Hi-index	14.99

Visualization

Abstract

A description of an architecture capable of computing two-dimensional fast Fourier transforms on a 256*256 pixel image at a rate of 30 images per second is presented. The architecture consists of a small number of basic building blocks which may be repeated to yield any desired performance. To achieve video rate performance, 16 butterfly processors, arranged as four coupled clusters of four processors each, and nine working memories are required. Because of the parallelism and pipelining used in the design, the system clock needed to achieve this high level of performance is only 240 ns.