Computer - IEEE Centennial: the state of computing
VLSI circuit testing using and adaptive optimization model
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Confidence analysis for defect-level estimation of VLSI random testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Bayesian statistical model checking with application to Simulink/Stateflow verification
Proceedings of the 13th ACM international conference on Hybrid systems: computation and control
Bayesian statistical model checking with application to Stateflow/Simulink verification
Formal Methods in System Design
| Hi-index | 14.98 |
A method for determining the optimal testing period and measuring the production yield is discussed. With the increased complexity of VLSI circuits, testing has become more costly and time-consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off the cost of testing and the penalty of passing a bad chip as good. The optimal testing period is first derived, assuming the production yield is known. Since the yield may not be known a priori, an optimal sequential testing strategy which estimates the yield based on ongoing testing results, which in turn determines the optimal testing period, is developed next. Finally, the optimal sequential testing strategy for batches in which N chips are tested simultaneously is presented. The results are of use whether the yield stays constant or varies from one manufacturing run to another.