Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2/sup /n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an inductive definition of a sequence with these properties, a succession of algorithms yielding the logic circuit of a next-state generator for the sequence is developed. Proving these algorithms equivalent demonstrates the correctness of the circuit rigorously.