Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays

Authors:
Sy-Yen Kuo;Sheng-Chiech Liang
Affiliations:
-;-
Venue:
IEEE Transactions on Computers
Year:
1992

Citing 4
Cited 0

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Fault-tolerance in balanced sorting networks

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High yield and reliable sorting networks for VLSI and WSI implementations

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The art of computer programming, volume 3: (2nd ed.) sorting and searching

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Abstract

A novel approach to online error detection and correction for high-throughput VLSI sorting arrays is presented. The error model is defined at the sorting element level and both functional errors and data errors are considered. Functional errors are detected and corrected by exploiting inherent properties as well as newly discovered special properties of the sorting array. Coding techniques are used to locate data errors. All the checkers are designed to be totally self-checking and hence the sorting array is highly reliable. Two-level pipelining is employed, making the design very efficient and suitable for real-time application. The structure is very regular and therefore is very attractive for VLSI or WSI implementation.