Microprocessors & Microsystems
Experiences in designing the M3 backplane bus standard
Microprocessors & Microsystems
Microcomputer Busses and Links
Microcomputer Busses and Links
Organization of systems with bussed interconnections
Organization of systems with bussed interconnections
| Hi-index | 14.98 |
A common misconception is that asynchronous binary arbitration settles in at most four units of bus-propagation delay, irrelevant of the number of arbitration bus lines. The author disproves this conjecture by presenting an arrangement of modules on m bus lines, for which binary arbitration requires /spl lsqb/m/2/spl rsqb/ units of bus-propagation delay to settle. He also proves that for any arrangement of modules on m bus lines, binary arbitration settles in at most /spl lsqb/m/2/spl rsqb/+2 units of bus-propagation delay.