Reduction Operations on a Distributed Memory Machine with a Reconfigurable Interconnection Network

  • Authors:
  • S. Miguet;Y. Robert

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Parallel and Distributed Systems
  • Year:
  • 1992

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Abstract

Performing reduction operations with distributed memory machines whose interconnection networks are reconfigurable is considered. The focus is on machines whose interconnection graph can be configured as any graph of maximum degree d. The best way of interconnecting the p processors as a function of p,d and some problem- andmachine-dependent parameters that characterize the ratio communication/arithmetic forthe reduction operation are discussed. Experiments on transputer-based networks are ingood accordance with the theoretical results.