Performance Metrics for Embedded Parallel Pipelines
IEEE Transactions on Parallel and Distributed Systems
Parallel Structure in an Integrated Speech-Recognition Network
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
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A new architecture is presented to support the general class of real-timelarge-vocabulary speaker-independent continuous speech recognizers incorporatinglanguage models. Many such recognizers require multiple high-performance centralprocessing units (CPU's) as well as high interprocessor communication bandwidth. Thisarray processor provides a peak CPU performance of 2.56 giga-floating point operationsper second (GFLOPS) as well as a high-speed communication network. In order toefficiently utilize these resources, algorithms were devised for partitioning speech modelsfor mapping into the array processor. Also, a novel scheme is presented for a functionalpartitioning of the speech recognizer computations. The recognizer is functionallypartitioned into six stages, namely, the linear predictive coding (LPC) based featureextractor, mixture probability computer, (phone) state probability computer, wordprobability computer, phrase probability computer, and traceback computer. Each ofthese stages is further subdivided as many times as necessary to fit the individualprocessing elements (PE's). The functional stages are pipelined and synchronized with the frame rate of the incoming speech signal. This partitioning also allows a multistage stack decoder to be implemented for reduction of computation.