Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
VirtualClock: a new traffic control algorithm for packet-switched networks
ACM Transactions on Computer Systems (TOCS)
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Moore's law: past, present, and future
IEEE Spectrum
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ATM Input-Buffered Switches with the Guaranteed-Rate Property
ISCC '98 Proceedings of the Third IEEE Symposium on Computers & Communications
Providing qos guarantees in input-buffered crossbar switches with speedup
Providing qos guarantees in input-buffered crossbar switches with speedup
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
VOIQ: A Practical High-Performance Architecture for the Implementation of Single-Buffered Routers
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
JumboGen: dynamic jumbo frame generation for network performance scalability
ACM SIGCOMM Computer Communication Review
Towards low-complexity Internet traffic engineering: The Adaptive Multi-Path algorithm
Computer Networks: The International Journal of Computer and Telecommunications Networking
Best Effort and Priority Queuing Policies for Buffered Crossbar Switches
SIROCCO '08 Proceedings of the 15th international colloquium on Structural Information and Communication Complexity
Strong performance guarantees for asynchronous buffered crossbar scheduler
IEEE/ACM Transactions on Networking (TON)
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Latency equalization as a new network service primitive
IEEE/ACM Transactions on Networking (TON)
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Most high performance routers today use combined input and output queueing (CIOQ). The CIOQ router is also frequently used as an abstract model for routers: at one extreme is input queueing, at the other extreme is output queueing, and in-between there is a continuum of performance as the speedup is increased from 1 to N (where N is the number of linecards). The model includes architectures in which a switch fabric is sandwiched between two stages of buffering. There is a rich and growing theory for CIOQ routers, including algorithms, throughput results and conditions under which delays can be guaranteed. But there is a broad class of architectures that are not captured by the CIOQ model, including routers with centralized shared memory, and load-balanced routers. In this paper we propose an abstract model called Single-Buffered (SB) routers that includes these architectures. We describe a method called Constraint Sets to analyze a number of SB router architectures. The model helped identify previously unstudied architectures, in particular the Distributed Shared Memory router. Although commercially deployed, its performance is not widely known. We find conditions under which it can emulate an ideal shared memory router, and believe it to be a promising architecture. Questions remain about its complexity, but we find that the memory bandwidth, and potentially the power consumption of the router is lower than for a CIOQ router.