The fast Fourier transform and its applications
The fast Fourier transform and its applications
Fundamentals of speech recognition
Fundamentals of speech recognition
Logic synthesis using Synopsys (2nd ed.)
Logic synthesis using Synopsys (2nd ed.)
Discrete Time Processing of Speech Signals
Discrete Time Processing of Speech Signals
Some Results on a SRT Type Division Scheme
IEEE Transactions on Computers
Measuring the Accuracy of ROM Reciprocal Tables
IEEE Transactions on Computers
Function Evaluation by Table Look-up and Addition
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Compensated mel frequency cepstrum coefficients
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 01
A VLSI chip for isolated speech recognition system
IEEE Transactions on Consumer Electronics
Critical Band Subspace-Based Speech Enhancement Using SNR and Auditory Masking Aware Technique
IEICE - Transactions on Information and Systems
TinyEARS: spying on house appliances with audio sensor nodes
Proceedings of the 2nd ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Building
Efficient FPGA implementation of a knowledge-based automatic speech classifier
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Hi-index | 0.00 |
The mel frequency cepstral coefficient (MFCC) is one of the most important features required among various kinds of speech applications. In this paper, the first chip for speech features extraction based on MFCC algorithm is proposed. The chip is implemented as an intellectual property, which is suitable to be adopted in a speech recognition system on a chip. The computational complexity and memory requirement of MFCC algorithm are analyzed in detail and improved greatly. The hybrid table look-up scheme is presented to deal with the elementary function value in the MFCC algorithm. Fixed-point arithmetic is adopted to reduce the cost under the accuracy studies of finite word length effect. Finally, the area-efficient design is implemented successfully into the single Xilinx XC4062XL FPGA.