Exploiting bit level concurrency in real-time geometric feature extractions

• Authors: W. Liu;T.-F. Yeh;W. E. Batchelor;R. Cavin
• Venue: ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
• Year: 1988

Geometric feature extraction can be characterized as a computationally intensive task in the environment of real-time automated vision systems requiring algorithms with a high degree of parallelism and pipelining under the raster-scan I/O constraint. Using divide-and-conquer techniques, many feature extraction algorithms have been formulated as a pyramid and then as a binary tree structure. An efficient mapping from a tree structure into a pipelined array of 2logN, stages is presented for processing a NxN image. In the proposed mapping structure, the identification of the information growing property inherit in feature extraction algorithms allows us to exploit bit-level concurrency in the architectural design. Accordingly, the design of each staged pipelined processor is simplified.A single VLSI chip which can generate (p+1)(q+1) moments concurrently in real-time applications is reported. This chip posses a hardware complexity of &Ogr;(pq(p+q)log2N) where p, q stand for the orthogonal orders of the moment. This hardware complexity is an improvement over other reported methods &Ogr;(pq(p+q)2log2N).