Programming expert systems in OPS5: an introduction to rule-based programming
Programming expert systems in OPS5: an introduction to rule-based programming
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An architecture that captures some of the inherent parallelism of the OPS5 expert system language has been designed and implemented at Oak Ridge National Laboratory. A central feature of this architecture is a network bus over which a single host processor broadcasts messages to a set of parallel rule processors. This transmit-only bus is implemented by a memory-mapped scheme which permits the rule processors to be decoded in parallel. All OPS5 rule matching processes and most of the processes associated with conflict resolution are executed by the parallel rule processors. The host performs the tasks associated with the firing of a rule selected by the conflict resolution process. Performance data are presented for the prototype system which comprises a host processor and 64 parallel rule processors, each embodying a Motorola MC68000 microprocessor and 512 Kbytes of unshared memory.