Is 32 bits of address too much?
ACM SIGARCH Computer Architecture News
Starting FORTH
Two-level hybrid interpreter/native code execution for combined space-time program efficiency
SIGPLAN '87 Papers of the Symposium on Interpreters and interpretive techniques
Peering through the RISC/CISC fog: an outline of research
ACM SIGARCH Computer Architecture News
On the design of Always Compatible Instruction Set Architecture(ACISA)
ACM SIGARCH Computer Architecture News
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The following computer architecture offers extensible machine language. That is it has an open-ended instruction set. It does this by using the same format for both op-codes and subroutine calls. Theoretically this means that the programmer can chose an instruction set for the application at hand. Ie., the machine language representation of a program can correspond to a high level textual representation or a program.The mechanism of instruction processing for this architecture is essentially a way of encompassing the major categories of interpreters : Direct threaded code, indirect threaded code, and P-code or compressed threaded code. The mechanism is closest in spirit to that of Forth and can be considered a hardware implementation of Forth.Due to the simplicity of instruction set representation, the design is not tied to any one word size. Thus, it is implementable on all the major word sizes (16, 24, 32, 36, 48, 60, or 64 bits).I hope this is perceived as an elegant design.