Contrasting characteristics and cache performance of technical and multi-user commercial workloads
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Memory system characterization of commercial workloads
Proceedings of the 25th annual international symposium on Computer architecture
Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
Proceedings of the 25th annual international symposium on Computer architecture
Execution characteristics of desktop applications on Windows NT
Proceedings of the 25th annual international symposium on Computer architecture
Performance of database workloads on shared-memory systems with out-of-order processors
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
DBMSs on a Modern Processor: Where Does Time Go?
VLDB '99 Proceedings of the 25th International Conference on Very Large Data Bases
Performance Characterization of the Pentium® Pro Processor
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
POWER3: the next generation of PowerPC processors
IBM Journal of Research and Development
A multithreaded PowerPC processor for commercial servers
IBM Journal of Research and Development
Method-level phase behavior in java workloads
OOPSLA '04 Proceedings of the 19th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
A performance counter architecture for computing accurate CPI components
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Performance of commercial multimedia workloads on the Intel Pentium 4: A case study
Computers and Electrical Engineering
Optimizing the datacenter for data-centric workloads
Proceedings of the international conference on Supercomputing
An efficient CPI stack counter architecture for superscalar processors
Proceedings of the great lakes symposium on VLSI
| Hi-index | 4.10 |
Today's superscalar microprocessors tend to execute instructions in an order different from the instruction sequence fed to them. With the aid of sophisticated branch predictors, they identify the program flow's potential path to find instructions that can be executed in advance.CPU-intensive benchmarks have been widely used to evaluate these processors. The authors report a study demonstrating that to maximize performance on Internet server applications, modern processor architectures need further enhancements and optimizations, particularly in memory system design.