Fault Injection Experiments Using FIAT
IEEE Transactions on Computers
FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior Under Faults
IEEE Transactions on Software Engineering - Special issue on software reliability
Reaching Agreement in the Presence of Faults
Journal of the ACM (JACM)
On-Line Monitoring: A Tutorial
Computer
Economic Online Self-Test in the Time-Triggered Architecture
IEEE Design & Test
An Evaluation of the Error Detection Mechanisms in MARS Using Software-Implemented Fault Injection
EDCC-2 Proceedings of the Second European Dependable Computing Conference on Dependable Computing
Can Software Implemented Fault-Injection Be Used on Real-Time Systems?
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Bus Architectures for Safety-Critical Embedded Systems
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Avoiding the Babbling-Idiot Failure in a Time-Triggered Communication System
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
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Fault injection has become a valuable methodology for dependability evaluation of computer systems. Software implemented fault injection is used because of the relative simplicity of injecting faults. In this paper we present a methodology for assessment of the error detection mechanisms of the Time-Triggered Architecture (TTA) bus structure by emulating hardware faults using software implemented fault injection. The TTA is an architecture for distributed embedded safety-critical realtime applications which have high dependability requirements. At the core of the architecture is the time-triggered communication protocol TTP/C running on a dedicated communication controller. In the TTA fail-silence is a main concern, thus high error detection coverage with small error detection latency is required. Temporal intrusiveness of the software fault injector is measured and analyzed. A fault injection tool set for use in experimental assessment of newer chip implementations of the TTPC communication controller, is developed.