Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
IEEE Transactions on Software Engineering
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Dependability: Basic Concepts and Terminology
Dependability: Basic Concepts and Terminology
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Fault Tolerant Automotive Systems: An Overview
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
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This paper presents a simulation model of the Time-Triggered Protocol (TTP/C) based embedded computer system as a tool for evaluation of system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machineindependent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the TTP/C specification. These experiments were done within the EU/IST FIT (Fault Injection for Time triggered architecture) project solution.