Simulation semantics for min-max DEVS models
AIS'04 Proceedings of the 13th international conference on AI, Simulation, and Planning in High Autonomy Systems
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The design of VHDL transport delay uses an implicit assumption that bus with multiple taps, only one tap is a driver and the signal reaches the other taps delayed only by the time necessary for the electro-magnetic propagation. Perturbation due to reflection at the intermediate taps, is ignored and this results in incorrect timing behavior. This paper proposes extensions to VHDL grammar and defines new semantics in the language to accurately capture and model the transport timing behavior of buses with multiple, distinct taps.