Circuit Simulation on Shared-Memory Multiprocessors

  • Authors:
  • P. Sadayappan;V. Visvanathan

  • Affiliations:
  • Ohio State Univ., Columbus;AT&T Bell Laboratories, Murray Hill, NJ

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1988

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Abstract

Reports the parallelization on a shared-memory vector multiprocessor of the computationally intensive components of a circuit simulator-matrix assembly (including device model evaluation) and the unstructured sparse linear system solution. A theoretical model is used to predict the performance of the lock-synchronized parallel matrix assembly, and the results are compared to experimental measurements. Alternate approaches to efficient sparse matrix solution are contrasted, highlighting the impact of the matrix representation/access strategy on achievable performance, and medium-grained approach with superior performance is introduced. The techniques developed have been incorporated into a prototype parallel implementation of the production circuit simulator ADVICE on the Alliant FX/8 multiprocessor.