Hardware implementation issues of data prefetching
ICS '95 Proceedings of the 9th international conference on Supercomputing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Sequential Hardware Prefetching in Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
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Sequential prefetching is a classic method of prefetching cache contents. There are two variants of sequential prefetching. Prefetch-on-miss prefetches the next consecutive cache lines following the line that misses in the cache. Tagged prefetch prefetches the next consecutive lines of the cache line that is currently being accessed. In this paper, we compare these two variants both analytically and experimentally, and show that while tagged prefetch is better with smaller latencies, prefetch-on-miss is better when the memory latency is large.