An SoC Solution for Massive Parallel Processing

  • Authors:
  • David Reed;Raymond Hoare

  • Affiliations:
  • -;-

  • Venue:
  • IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
  • Year:
  • 2002

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Abstract

Through evaluating a major FPGA manufacturer, the concept of utilizing the parallelism of FPGA technology for massively parallel processing is examined. Currently, FPGA's contain over a hundred thousands logic elements, an array of over 256 embedded memory banks and a complex interconnection network. This paper presents a detailed analysis of a particular FPGA device, available pre-device hardware blocks and shows how a massively parallel system can be constructed. Finally, a simple design illustrating the usage of FPGA resources, performance, and parallelism is presented.