HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Parallel Algorithm Design with Coarse-Grained Synchronization
ICCS '01 Proceedings of the International Conference on Computational Science-Part II
A Software Design Model for Parallel Applications on Heterogeneous Systems
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
WAE '01 Proceedings of the 5th International Workshop on Algorithm Engineering
Emulations between QSM, BSP and LogP: a framework for general-purpose parallel algorithm design
Journal of Parallel and Distributed Computing
Hi-index | 0.00 |
Parallel programming models should attempt to satisfy two conflicting goals. On one hand, they should hide architectural details so that algorithm designers can write simple, portable programs. On the other hand, models must expose architectural details so that designers can evaluate and optimize the performance of their algorithms. In this paper, we experimentally examine the trade-offs made by a simple shared-memory model, QSM, to address this dilemma. The results indicate that analysis under the QSM model yields quite accurate results for reasonable input sizes and that algorithms developed under QSM achieve performance close to that obtainable through more complex models, such as BSP and LogP.