The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
The DARPA image understanding benchmark for parallel computers
Journal of Parallel and Distributed Computing
Parallel architectures and algorithms for image understanding
Parallel architectures and algorithms for image understanding
SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Computer
Hi-index | 0.00 |
Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the "on-chip multiprocessor" has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively.