Simulated annealing and Boltzmann machines: a stochastic approach to combinatorial optimization and neural computing
Parallel Random Number Generation for VLSI Systems Using Cellular Automata
IEEE Transactions on Computers
Parallel simulated annealing techniques
Emergent computation
Allocating hard real-time tasks: an NP-hard problem made easy
Real-Time Systems
A Parallel Simulated Annealing Algorithm with Low Communication Overhead
IEEE Transactions on Parallel and Distributed Systems
Synchronous and Asynchronous Parallel Simulated Annealing with Multiple Markov Chains
IEEE Transactions on Parallel and Distributed Systems
Local Search in Combinatorial Optimization
Local Search in Combinatorial Optimization
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a concept of a CPU kernel with hardware support for local-search based optimization algorithms like Simulated Annealing (SA) and Tabu-Search (TS). The special hardware modules are: (i) A link ed-list memory representing the problem space. (ii) CPU instruction set extensions supporting fast moves within the neigh borhood of a solution. (iii) Support for the generation of moves for both algorithms, SA and TS. (iv) A solution mover managing several solution memories according to the optimization progress. (v) Hardware addressing support for the calculation of cost functions. (vi) Support for nonlinear functions in the acceptance procedure of SA. (vii) A status module providing on-line information about the solution quality. (v) An acceptance prediction module supporting parallel SA algorithms. Simulations of a VHDL implementation show a speedup of up to 260 in comparison to an existing implementation without hardware support.