Hardware Support for 3D Cellular Processing
PaCT '97 Proceedings of the 4th International Conference on Parallel Computing Technologies
FPGA Implementations of the Massively Parallel GCA Model
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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The configurable coprocessor CEPRA-1X was developed as a PC plug-in card in order to speed up cellular processing significantly. Cellular Processing is an attractive and simple massive parallel processing model. To increase its general acceptance and usability it must be supported by a software environment, an efficient simulator and a special language. For this purpose the cellular description language CDL was defined and implemented. With CDL complex cellular algorithms can be described in a concise and readable form. A CDL program can automatically be transformed into a logical design for the CEPRA-1X. The design is loaded into field programmable gate arrays for the computation of the state transition of the cells. For time dependent or complex rules the design may be reconfigured between consecutive generations. An example is presented to show the generation of logic code.