MIND execution by SIMD computers
Journal of Information Processing
A framework for balancing control flow and predication
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Integrated predicated and speculative execution in the IMPACT EPIC architecture
Proceedings of the 25th annual international symposium on Computer architecture
Programming languages and their compilers: Preliminary notes
Programming languages and their compilers: Preliminary notes
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
Compiler and runtime support for predictive control of power and cooling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
| Hi-index | 0.00 |
The next generation of microprocessors, particularly IA64, will incorporate hardware mechanisms for instruction-level predication in support of speculative parallel execution. However, the compiler technology proposed in support of this speculation is incapable of speculating across loops or procedural boundaries (function call and return). In this paper, we describe compiler technology that can support instruction-level speculation across arbitrary control flow and procedural boundaries. Our approach is based on the concept of converting a conventional control flow graph into a meta state graph in which each meta state represents a set of original states speculatively executed together.