The Aurora or-parallel Prolog system
New Generation Computing - Selected papers on parallel logic programming from the International Conference on Fifth Generation Computer Systems, 1988
Andorra I: a parallel Prolog system that transparently exploits both And-and or-parallelism
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
Flexible scheduling of or-parallelism is Aurora: the Bristol scheduler
PARLE '91 Proceedings on Parallel architectures and languages Europe : volume II: parallel languages: volume II: parallel languages
The detection and elimination of useless misses in multiprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Strategies for scheduling and- and or- work in parallel logic programming systems
ILPS '94 Proceedings of the 1994 International Symposium on Logic programming
An evaluation of Penny: a system for fine grain implicit parallelism
PASCO '97 Proceedings of the second international symposium on Parallel symbolic computation
Evaluating parallel logic programming systems on scalable multiprocessors
PASCO '97 Proceedings of the second international symposium on Parallel symbolic computation
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory Performance of Prolong Architectures
Memory Performance of Prolong Architectures
The DASH Prototype: Logic Overhead and Performance
IEEE Transactions on Parallel and Distributed Systems
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Optimising Parallel Logic Programming Systems for Scalable Machines
Euro-Par '98 Proceedings of the 4th International Euro-Par Conference on Parallel Processing
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
SS '95 Proceedings of the 28th Annual Simulation Symposium
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
| Hi-index | 0.00 |
In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.