Prime numbers and computer methods for factorization
Prime numbers and computer methods for factorization
How to prove yourself: practical solutions to identification and signature problems
Proceedings on Advances in cryptology---CRYPTO '86
On an implementation of the Mohan-Adiga algorithm
EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
A New \mathcal{NP}-Complete Problem and Public-Key Identification
Designs, Codes and Cryptography
An Integrity Check Value Algorithm for Stream Ciphers
CRYPTO '93 Proceedings of the 13th Annual International Cryptology Conference on Advances in Cryptology
ESIGN: an efficient digital signature implementation for smart cards
EUROCRYPT'91 Proceedings of the 10th annual international conference on Theory and application of cryptographic techniques
RSA moduli with a predetermined portion: techniques and applications
ISPEC'08 Proceedings of the 4th international conference on Information security practice and experience
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This paper describes results and experiences gained from the test implementation of an interactive identification scheme. It was intended to exploit the feasibility of an asymmetric crypto protocol for a state-of-the-art smart card environment. For that reason the identification scheme proposed by Fiat and Shamir was implemented between an actual smart card microprocessor and an industry standard personal computer with a smart card interface. The limits of a current smart card processor in terms of volatile and nonvolatile memory capacity and instruction set turned out to be a rather strict limitation for the choice of the algorithms used. The most time consuming task during the protocol is modular multiplication. Due to the processor structure it is performed as separate multiplication and reduction, where reduction is led back to integer multiplication. The current implementation allows the authentication of a 120 byte identification string at a security level of 2-20 within an average time of about 6 seconds. The experiences gained during this implementation led to a set of requirements for a future specialised processor for asymmetric cryptographic protocols that will be needed to increase this performance by some orders of magnitude.