Performance Evaluation of the Hitachi SR8000 Using OpenMP Benchmarks
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Bottleneck identification and scheduling in multithreaded applications
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
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This paper describes the implementation and evaluation of the OpenMP compiler designed for the Hitachi SR8000 Super Technical Server. The compiler performs parallelization for the shared memory multiprocessors within a node of SR8000 using the synchronization mechanism of the hardware to perform high-speed parallel execution. To create an optimized code, the compiler can perform optimizations across inside and outside of a PARALLEL region or can produce a code optimized for a fixed number of processors according to the compile option. For user's convenience, it supports combination of OpenMP and automatic parallelization or Hitachi proprietary directive and also supports reporting diagnostic messages which help user's parallelization. We evaluate our compiler by parallelizing NPB2.3-serial benchmark with OpenMP. The result shows 5.3 to 8.0 times speedup on 8 processors.