The multiscalar architecture
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Multiple-block ahead branch predictors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Trace cache: a low latency approach to high bandwidth instruction fetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Speculative multithreaded processors
ICS '98 Proceedings of the 12th international conference on Supercomputing
ICS '98 Proceedings of the 12th international conference on Supercomputing
Execution characteristics of desktop applications on Windows NT
Proceedings of the 25th annual international symposium on Computer architecture
Threaded multiple path execution
Proceedings of the 25th annual international symposium on Computer architecture
A dynamic multithreading processor
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Data speculation support for a chip multiprocessor
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Performance Study of a Concurrent Multithreaded Processor
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A dynamic multithreading processor
A dynamic multithreading processor
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Simultaneous multithreading (SMT) processors achieve high performance by executing independent instructions from different programs simultaneously [1]. However, the SMT model doesn't help single-thread applications and performs at its full potential only when executing multithreaded applications or multiple programs. Moreover, to minimize the total execution time of one selected high priority thread, that thread has to run alone. Recently, several speculative multithreading architectures have been proposed that exploit far away instruction level parallelism in single-thread applications. In particular, the dynamic multithreading or DMT model [2] uses hardware mechanisms to fork speculative threads at procedure and loop boundaries along the execution path of a single program, and executes these threads on a multithreaded processor. In this paper, we explore the performance scope of an SMT architecture in which spare thread contexts are used to support the DMT execution of procedure and loop threads. We show two significant advantages of this approach: (1) it increases processor utilization and total execution throughput when few programs are running, and (2) it eliminates or reduces the performance degradation of one selected high priority program when running simultaneously with other programs, without reducing total SMT throughput.