An experiment in automatic generation of test suites for protocols with verification technology
Science of Computer Programming - Special issue on COST 247, verification and validation methods for formal descriptions
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Verification and test generation for the SSCOP protocol
Science of Computer Programming
OPEN/CÆSAR: An OPen Software Architecture for Verification, Simulation, and Testing
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Using On-The-Fly Verification Techniques for the Generation of test Suites
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
IWTCS Proceedings of the IFIP TC6 11th International Workshop on Testing Communicating Systems
Specifying Hardware Systems in LOTOS
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
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We present an experiment which has demonstrated that methods and tools developed in the context of black box conformance testing of communication protocols can be efficiently used for testing the cache coherency protocol of a hardware multi-processor architecture. We have used the automatic conformance tests generator TGV developed by INRIA to generate abstract tests and we have developed a software in order to make them executable in the real test environment of Bull. The TGV approach has been considered by the hardware testing community as a serious alternative to usual random test generation. It overwhelms the well known debugging and coverage problems linked to this kind of technic.