Skewed associativity enhances performance predictability
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Eliminating cache conflict misses through XOR-based placement functions
ICS '97 Proceedings of the 11th international conference on Supercomputing
Trading conflict and capacity aliasing in conditional branch predictors
Proceedings of the 24th annual international symposium on Computer architecture
The design and performance of a conflict-avoiding cache
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Randomized Cache Placement for Eliminating Conflicts
IEEE Transactions on Computers - Special issue on cache memory and related problems
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Skewed Associativity Improves Program Performance and Enhances Predictability
IEEE Transactions on Computers
A Comparison of Locality-Based and Recency-Based Replacement Policies
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB
IEEE Transactions on Computers
Skewed caches from a low-power perspective
Proceedings of the 2nd conference on Computing frontiers
Generating cache hints for improved program efficiency
Journal of Systems Architecture: the EUROMICRO Journal
YAARC: yet another approach to further reducing the rate of conflict misses
The Journal of Supercomputing
Compiler techniques for reducing data cache miss rate on a multithreaded architecture
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Data layout for cache performance on a multithreaded architecture
Transactions on high-performance embedded architectures and compilers III
A cache design for probabilistically analysable real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
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