High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
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Input queued and combined input/output queued switching-architectures must be controlled by a scheduling algorithm, which solves contention in the transfer of data units to switch outputs. We consider the case of packet switches (or routers), i.e., devices operating on variable-size data units at their interfaces, assuming that they internally operate on fixed-size data units, and we propose novel extensions of known schedulinga lgorithms for input queued and combined input/output queued architectures. We show by simulation that such architectures can provide performance advantages over traditional output queued architectures.