Multiprocessor Clustering for Embedded Systems

Authors:
Vida Kianzad;Shuvra S. Bhattacharyya
Affiliations:
-;-
Venue:
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Year:
2001

Citing 9
Cited 1

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Abstract

In this paper, we address two key trends in the synthesis of implementations for embedded multiprocessors -- (1) the increasing importance of managing interprocessor communication (IPC) in an efficient manner, and (2) the acceptance of significantly longer compilation time by embedded system designers. The former aspect is evident in the increasing interest among embedded system architects in innovative communication architectures, such as those involving optical interconnection technologies, and hybrid electro-optical structures [7]. The latter aspect results because embedded multiprocessor systems are typically designed as final implementations for dedicated functions. While multiprocessor mapping strategies for general-purpose systems are usually designed with low to moderate complexity as a constraint, embedded system design tools are allowed to employ more thorough and time-consuming optimization techniques.