Parallel Algorithms and Architectures
Parallel Algorithms and Architectures
IEEE Transactions on Parallel and Distributed Systems
Scheduling Task Graphs on Arbitrary Processor Architectures Considering Contention
HPCN Europe 2001 Proceedings of the 9th International Conference on High-Performance Computing and Networking
SPDP '95 Proceedings of the 7th IEEE Symposium on Parallel and Distributeed Processing
A Performance Evaluation of CP List Scheduling Heuristics for Communication Intensive Task Graphs
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Benchmarking the Task Graph Scheduling Algorithms
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Comparison of Contention Aware List Scheduling Heuristics for Cluster Computing
ICPPW '01 Proceedings of the 2001 International Conference on Parallel Processing Workshops
A Realistic Model and an Efficient Heuristic for Scheduling with Heterogeneous Processors
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
ODBASE'06/OTM'06 Proceedings of the 2006 Confederated international conference on On the Move to Meaningful Internet Systems: CoopIS, DOA, GADA, and ODBASE - Volume Part II
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Static scheduling is the temporal and spatial mapping of a program to the resources of a parallel system. Scheduling algorithms use the Directed Acyclic Graph (DAG) to represent the sub-tasks and the precedence-constraints of the program to be parallelised. This article proposes an extention to the classical list scheduling heuristic that allows to schedule DAGs to arbitrary processor architectures considering link contention. In this extension, communication links are treated as shared resources likewise the processors and we improve the extended algorithm by exploiting unused time slots on the resources. The algorithm is experimentally compared to the existing heuristics BSA and DLS.