Performances of a Dynamic Threads Scheduler

Authors:
Smaïl Niar;Mahamed Adda
Affiliations:
-;-
Venue:
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Year:
2001

Citing 3
Cited 0

Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A Single-Chip Multiprocessor

Computer
Exploiting Speculative Thread-Level Parallelism on a SMT Processor

HPCN Europe '99 Proceedings of the 7th International Conference on High-Performance Computing and Networking

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the design and development of a dynamic scheduler of parallel threads in the Multithreaded multiProcessor Architecture (MPA). The scheduler relies on an on-chip associative memory whose management time is overlapped with the execution of ready threads. The scheduler efficiently assigns resources to threads, and permits them to communicate with great flexibility. The results achieved with small number of threads from programs with high degree of parallelism are very satisfactory, even under various degrees of cache misses.