The MIT Alewife machine: architecture and performance
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ICS '90 Proceedings of the 4th international conference on Supercomputing
The DASH Prototype: Logic Overhead and Performance
IEEE Transactions on Parallel and Distributed Systems
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Shared-Memory Implementation of an Irregular Particle Simulation Method
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing - Volume I
SPLASH: Stanford parallel applications for shared-memory
SPLASH: Stanford parallel applications for shared-memory
Operating system data structures for shared memory mimd machines with fetch-and-add
Operating system data structures for shared memory mimd machines with fetch-and-add
The NYU Ultracomputer Designing an MIMD Shared Memory Parallel Computer
IEEE Transactions on Computers
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
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The SB-PRAM is a shared memory machine which hides latency by simple interleaved context switching and which can be expected to behave almost exactly like a PRAM if all threads can be kept busy. We report measured run times of various versions of the MP3D benchmark on the completed hardware of a 64 processor SB-PRAM. The main findings of these experiments are: 1) parallel efficiency is 79% for 32 processors and 56% for 64 processors. 2) Parallel efficiency is limited by the number of available threads.