Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Hypernode reduction modulo scheduling
Proceedings of the 28th annual international symposium on Microarchitecture
Hamiltonian Recurrence for ILP
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
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Instruction Scheduling is the task of deciding what instruction will be executed at which unit of time. The objective is to extract maximum instruction level parallelism for the code. Compilers designed for VLIW and EPIC architectures do static instruction scheduling in a back-end pass. This pass, known as scheduler, needs to have full knowledge of the execution time of each instruction. But memory access instructions have a variable latency, depending on their locality and the memory hierarchy architecture. The scheduler must assume a constant value, usually the execution time assigned to a hit. At execution a miss may reduce the parallelism because idle cycles may appear before the instructions that need the data. This paper describes a statistic model to evaluate how sensitive are the scheduling algorithms to the variable time operations. We present experimental measures taken over two static scheduling algorithms based on software pipelining.