POPL '88 Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The cache performance and optimizations of blocked algorithms
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Compiling for numa parallel machines
Compiling for numa parallel machines
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Reuse-Driven Tiling for Data Locality
LCPC '97 Proceedings of the 10th International Workshop on Languages and Compilers for Parallel Computing
Buffer and Register Allocation for Memory Space Optimization
Journal of VLSI Signal Processing Systems
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This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Due to the particular characteristics of I/O operations, straightforward extension of the traditional tiling method to I/O-intensive programs may result in poor I/O performance. Therefore, the technique proposed in this paper customizes iteration space tiling for high I/O performance. The generated code results in huge savings in the number of I/O calls as well as the data volume transferred between the disk subsystem and main memory.