IEEE Transactions on Computers
IEEE Transactions on Computers
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Estimating the execution time distribution for a task graph in a heterogeneous computing system
HCW '97 Proceedings of the 6th Heterogeneous Computing Workshop (HCW '97)
HCW '97 Proceedings of the 6th Heterogeneous Computing Workshop (HCW '97)
COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Communication nets; stochastic message flow and delay
Communication nets; stochastic message flow and delay
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In this paper, we propose a stochastic model for hardware software cosynthesis of a heterogeneous, multiprocessor computing system dedicated for a specified real time application. In this model, the task execution times and the data transfer times are taken to be random variables. Based on the stochastic framework, we derive a method for generating optimum task schedules and evaluating the performance of the architecture. The pool of resources required for building the architecture and the task allocations are optimized by a genetic algorithm. We demonstrate that this approach produces architectures which are superior in terms of cost and processor utilization. Moreover, it yields good solutions even in situations where no feasible solution could be produced using deterministic timings. The scheduling algorithm has a polynomial time complexity. The components of the architecture are evolved in a hierarchical manner, progressively refining it by applying the genetic algorithm in distinct phases. This provides a powerful CAD tool for cosynthesis which can generate a range of optimum solutions with exchangeable cost and performance benefits.