A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

Authors:
José Luis Rossello;Jaume Segura
Affiliations:
-;-
Venue:
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Year:
2002

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Abstract

We provide an accurate analytical expression for the propagation delay and the output transition time of submicron CMOS buffers that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in deep-submicron technologies. The model is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.35碌m and a 0.18碌m process technologies show significant improvements over previously-published models.