The existence of refinement mappings
Theoretical Computer Science
Synchronous programming with events and relations: the SIGNAL language and its semantics
Science of Computer Programming
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Translation Validation for Synchronous Languages
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Operational and Compositional Semantics of Synchronous Automaton Compositions
CONCUR '92 Proceedings of the Third International Conference on Concurrency Theory
A Provably Correct Embedded Verifier for the Certification of Safety Critical Software
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
SAS'10 Proceedings of the 17th international conference on Static analysis
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Translation validation is an alternative to the verification of translators (compilers, code generators). Rather than proving in advance that the compiler always produces a target code which correctly implements the source code (compiler verification), each individual translation (i.e. a run of the compiler) is followed by a validation phase which verifies that the target code produced on this run correctly implements the submitted source program. In order to be a practical alternative to compiler verification, a key feature of this validation is its full automation. In this paper we demonstrate the feasibility of translation validation for industrial code generators from DC+ -a widely used intermediate format for synchronous languages- to C. We explain the compilation pattern from DC+ to C and advocate new abstraction techniques for a fragment of first order logic as part of the automation of our approach.