Using Formal Verification Techniques to Reduce Simulation and Test Effort

Authors:
Odile Laurent;Pierre Michel;Virginie Wiels
Affiliations:
-;-;-
Venue:
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Year:
2001

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Abstract

This paper describes an experiment in using formal methods in an industrial context. The goal is to use formal verification techniques in order to alleviate the simulation and test activities. The application is a flight control computer of the Airbus A340.